Digital Signal Processors (DSP) are frequently incorporated into modern integrated circuits due to the flexibility and reliability provided in these processing circuits. DSP circuits are used to implement complex audio functions such as echo cancellation, audio equalization effects, and encoding. In some applications, it is desirable to digitally process an analog signal using the DSP. For example, it may be desirable to capture, process, and reproduce an external audio source, such as a human voice or music. This audio signal must first be captured as an analog signal, typically using a microphone, and then converted to a digital format prior to processing in the DSP circuit. An analog-to-digital converter (ADC) is typically used for the conversion step. This ADC must accurately convert the audio signal, without distortion, to maintain High-Fidelity (Hi-Fi) audio quality throughout the signal path.
In portable electronic devices where external audio is captured and processed, an important issue is the potential for large variation of audio input amplitude as recording conditions change. For example, the distance between the microphone and the audio source may vary over time. Large amplitude variation creates conflicting requirements for the ADC and makes it difficult to maintain high quantization precision over a wide-dynamic range. A common solution to this problem is to subject the analog input signal to a programmable-gain amplifier (PGA) prior to the ADC. A PGA is designed to maintain at its output a fixed amplitude analog voltage invariant of fluctuations in the amplitude of the analog input signal. To achieve this effect, an automatic level control (ALC) algorithm monitors the digital code produced by the ADC and alters the gain of the PGA so as, ideally, to maintain a fixed input amplitude to the ADC. With the ADC signal now at a fixed level above the quantization noise, the conflicting requirements on the ADC are eased.
An example of a prior art programmable-gain amplifier circuit 500 is illustrated in a circuit schematic block diagram in FIG. 6. The circuit 500 includes an operation amplifier 510, a series of resistors 532, 534, and 536, and switches 540 and 544. With either of the switches SW1 540 or SW2 544 closed, a feedback path is created from the amplifier output VOUT 528 to the non-inverting amplifier input. This feedback path creates a gain function from the signal input VIN 520 to the output VOUT 528. For example, if switch SW1 540 is closed while SW2 544 is open, then transfer gain is found to be VOUT/VIN=−(R1+R2)/RIN. Where RIN=R1=R2, the resulting gain is −2 or +6 dB. Similarly, if switch SW1 540 is open while SW2 544 is closed, then transfer gain is found to be VOUT/VIN=−(R2)/(RIN+R1). Where RIN=R1=R2, the resulting gain is −½ or −6 dB. Therefore, the gain magnitude of the programmable gain amplifier circuit 500 can be varied from −6 dB to +6 dB by selectively closing or opening the switches. The gain resolution of the circuit 500 is defined as the minimum step to which the gain magnitude may be adjusted. Here, since there are only two states, the minimum step is +6 dB−(−6 dB) or 12 dB. Therefore the gain resolution is 12 dB. Gain resolution is an important parameter for audio quality. Fine gain resolution is desirable to avoid audible ALC gain changes.
Another prior art programmable gain amplifier circuit 600 is shown in FIG. 7. This circuit 600 improves the gain resolution by extending the resistor network to four resistors 632, 634, 636, and 638, and the switching network to three switches 640, 644, and 648. The total value of resistance in the feedback loop has not been altered. So no additional silicon area is required for resistors. However, an additional switch SW3 648 and switch control line are required. The transfer gain remains +6 dB for the case when SW1 540 is closed. Closing switch SW3 648 results in a gain of −6 dB (as was the case for the SW2 switch of the prior circuit). However, if SW2 644 is closed, the transfer gain is −1 or 0 dB. It can be seen that this circuit 600 is able to maintain a gain magnitude range of 12 dB, while generating a finer gain resolution of 6 dB. In general, better gain resolution may be achieved by adding additional resistors, switches, and control signals. However, if the total resistance is to be kept constant, then the unit size of each resistor must be reduced. This unit size reduction impairs resistor matching on the integrated circuit. Conversely, if the proper unit size is maintained, then the additional series resistors will consume significant silicon area. Hence, there is typically a trade-off between silicon area and gain resolution.
Gain resolution may also be improved through the use of a zero-crossing detector. A PGA utilising a zero-cross detector will only allow gain changes when the input audio signal is at minimum amplitude (i.e. zero). Any audible artifacts introduced by the gain variation are minimized due to the signal being at a minimum when the gain is changed. However, zero-cross detectors are undesirable for several reasons, including additional power and area requirements and significant circuit complexity. Furthermore, zero-cross detectors are susceptible to problems caused by offset in the signal path or absence of a signal. While noise gates can be used to alleviate these problems, noise gates limit the effective noise performance of the circuit.
Poor gain-resolution in the analog domain may also be compensated by including additional digital gain stages as in discussed in published U.S. Pat. Application 2005/0195448 to Llewellyn, et al. However, gain changes that occur after digital quantization do not experience the same dynamic range improvement as found in the analog domain due to the fixed signal-to-noise ratio of the digital stages. Further, the addition of the digital gain stages adds complexity to the ALC circuit, which must synchronize the gain changes to avoid audible distortion.
Another alternative for improving gain resolution is to periodically switch between the resistor ratios. Referring again to FIG.6, switches SW1 540 and SW2 544 may each be controlled by a pulse width modulated (PWM) signal. For example, if each switch were controlled by a PWM signal operating at the same % duty cycle, yet at opposite phases for each switch, then at any moment one switch is OFF while the other switch is ON. As a result, the variable gain would oscillate between +6 dB and −6 dB. If the PWM signals are set to 50%, the average gain of the circuit would be at the midpoint of the two gains, or 0 dB. If the period of the PWM is sufficiently short, then this average value of 0 dB would appear as the transfer gain of the PGA circuit 500 and there would be no audible artifacts. Further, the gain of such a PGA circuit can be varied between the maximum and minimum gains of +6 dB and −6 dB by varying the PWM duty cycle. This PWM approach does not require additional switches or control lines. However, due to the nature of the sliding resistor, the gain does not vary linearly. Rather, the gain varies logarithmically with the duty cycle. However, if fine resolution is desired, then a very high frequency clocking reference must be used. Integrated circuits are restricted in the maximum reference clock available due to power and circuit complexity constraints; thus limiting the gain-resolution practically achievable using only PWM.